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山口　憲　Ken YAMAGUCHI

山口　憲 アドバンスソフト株式会社
主管研究員

〒107-0052
東京都港区赤坂１丁目9番20号
第16興和ビル南館7階
アドバンスソフト株式会社　本社

学位

工学博士

略歴

1970年　横浜国立大学 工学部 電気工学科卒業
1972年　横浜国立大学大学院工学研究科修士課程修了
1972年　株式会社日立製作所入社 中央研究所並びに基礎研究所勤務
2007年5月　アドバンスソフト株式会社 主管研究員

学会および社会における活動

  1. 応用物理学会 正員
  2. 電子情報通信学会 正員
  3. 日本物理学会 正員
  4. IEEE (USA) Senior Member
  5. NASECODE Conference　第3回('83)～第6回('89)運営委員
  6. IEDM'86,　'87　論文委員
  7. 電子情報通信学会　論文査読委員
  8. 電子情報通信学会CPD部会　委員(平成15年～平成19年)
  9. 1991年度　広島大学講師(集積化システム研究センタ客員教授)
  10. 1994-2006年度　東京農工大学大学院非常勤講師
  11. 2002年度～　 明治大学兼任講師
  12. 2004年度～　東邦大学非常勤講師

メッセージ

30有余年、半導体デバイスシミュレーションに取り組んできました。シミュレーション技術は飛躍的に進歩し、ソフトウェアも使いやすく高機能になりました。

でも大切なことは何のために何を成すのかの目的意識です。シミュレーションを何のために行っているのか、出てきた結果は何を意味するのかをきちんと評価検証することが大切と考えています。

単にソフトウェアを提供するだけでなく、シミュレーションにおいて気を付けるべきことなどを広くお伝えできればと思っています。

書籍

  1. 冨澤一隆, 山口 憲, "セメスター大学講義 半導体デバイス －動作原理と応用－", 丸善株式会社, 平成15年3月30日発行
  2. K. Nakagawa and K. Yamaguchi, "Silicon atomic layer doping field-effect transistors (FETs)", a part of a book entitled "Delta-doping of semiconductors" edited by E. F. Schubert, Camblidge University Press, in 1996

業務・研究経歴

  1. 半導体デバイス物理、モデリング研究
  2. 半導体デバイス高性能、高信頼性設計研究
  3. シリコン半導体デバイスシミュレータの開発
  4. 化合物半導体電子デバイスシミュレータの開発
  5. 半導体光デバイスシミュレータの開発
  6. モンテカルロ法デバイスシミュレータの開発
  7. 半導体プロセス・デバイス・回路一貫シミュレータの開発
  8. 3次元汎用熱伝導プログラムの開発

発表論文

  1. T. Ohta and K. Yamaguchi, "Polarization of Core Fermion and the Heat Transport of Flux Line", J. Phys. Soc. Japan, vol. 31, no. 3, pp. 636 - 640, September, 1971
  2. K. Yamaguchi, T. Toyabe and H. Kodera, "Effect of Field-Dependent Carrier Diffusion on the Two-Dimensional Analysis of a Junction Gate FET", Japan. J. Appl. Phys., vol. 14, no. 7, pp. 1069 - 1070, July 1975
  3. K. Yamaguchi, T. Toyabe and H. Kodera, "Two-dimensional Analysis of Vertical Junction Gate FET's", Proc. 7th Conf. Solid State Devices, Tokyo, 1975, Supplement to Japan. J. Appl. Phys., vol. 15, pp. 163 - 168, 1976
  4. K. Yamaguchi, T. Toyabe and H. Kodera, "Two-dimensional Analysis of Triode-like Operation of Junction Gate FET's", IEEE Trans. Electron Devices, vol. ED-22, no. 11, pp. 1047 - 1049, 1975
  5. K. Yamaguchi and H. Kodera, "Drain Conductance of Junction Gate FET's" in the Hot Electron Range", IEEE Trans. Electron Devices, vol. ED-23, no. 6, pp. 545 - 553, June 1976
  6. K. Yamaguchi, S. Asai and H. Kodera, "Two-dimensional Numerical Analysis of Stability Criteria of GaAs FET's", IEEE Trans. Electron Devices, vol. ED-23, no. 12, pp. 1283 - 1290, Dec. 1976
  7. 山口 憲, 古寺 博, "２次元計算機シミュレ－ションによる３極管特性J-FETの高出力化のための最適設計" 電子通信学会論文誌(C), vol. J60-C, no. 7, pp. 407 - 414, 1977, 英文要約K. Yamaguchi and H. Kodera, "Design of Triode-Like High Power J-FET’S by Two-Dimensional Computer Simulation" Trans. Ins. Electronics and Communication Eng. Japan, vol. E60, no. 7, pp. 378 - 379, July 1977
  8. K. Yamaguchi and H. Kodera, "Optimum Design of Triode-like J-FET's by Two-dimensional Computer Simulation", IEEE Trans. Electron Devices, vol. ED-24, no. 8, pp. 1061 - 1069, August 1977
  9. K. Yamaguchi and S. Asai, "Excess Gate Current Analysis of Junction Gate FET's by Two-dimensional Computer Simulation", IEEE Trans. Electron Devices, vol. ED-25, no. 3, pp. 362 - 369, March 1978
  10. T. Toyabe, K. Yamaguchi, S. Asai and M. S. Mock, "A Numerical Model of Avalanche Breakdown in MOSFET's", IEEE Trans. Electron Devices, vol. ED-25, no. 7, pp. 825 - 832, July 1978
  11. K. Yamaguchi, "Field-Dependent Mobility Model for Two-Dimensional Numerical Analysis of MOSFET's", IEEE Trans. Electron Devices, vol. ED-26, no. 7, pp. 1068 - 1074, July 1979
  12. 鳥谷部 達, 山口 憲, 浅井 彰二郎, 古寺 博, 氏家 一彬, M. S. Mock, "MOS FET２次元数値解析の高速化と機能拡大" 電子通信学会論文誌(C), vol. J62-C, no. 12, pp. 826 - 833, 1979年12月, translated to English in Scripta Electoronica, "Rapid computation and extended analyzing functions in two-dimensional numerical analysis of MOS FET's" Trans. IECE Japan, vol. J62-C, no. 12, pp. 826 - 833, December 1979
  13. S. Ochi, T. Okabe,I. Yoshida, K. Yamaguchi and M. Nagata, "Computer analysis of breakdown mechanism in planar power MOSFET's", IEEE Trans. Electron Devices, vol. ED-27, no. 2, pp. 399 - 400, February 1980
  14. K. Narita and K. Yamaguchi, "IGFET hot electron emission model", Solid-State Electronics, vol. 23, pp. 721 - 725, 1980
  15. K. Yamaguchi, S. Takahashi and H. Kodera, "Theoretical study of a channel-doped separate gate Si MOSFET (SG-MOSFET) by two-dimensional computer simulation", IEEE Trans. Electron Devices, vol. ED-28, no. 1, pp. 117 - 120, January 1981
  16. K. Yamaguchi and S. Takahashi, "Theoretical characterization and high-speed performance evaluation of GaAs IGFETs", IEEE Trans. Electron Devices, vol. ED-28, no. 5, pp. 581 - 587, 1981
  17. K. Yamaguchi and S. Takahashi, "Submicron gate MOSFETs with channel-doped separate gate structures (SG-MOS FETs)", IEEE Trans. Electron Devices, vol. ED-28, no. 7, pp. 888 - 890, July 1981
  18. R. Kondo, K. Yamaguchi, Y. Yatsuda, S. Minami and Y. Itoh, "A model of write-inhibition in dynamic injection NMOS", IEEE Trans. Electron Devices, vol. ED-28, no. 7, pp. 849 - 854, July 1981
  19. K. Yamaguchi, Y. Shiraki, Y. Katayama and Y, Murayama, "A new short channel MOSFET with an atomic-layer-doped impurity-profile (ALD-MOSFET)", Proc. of the 14th Conf. (1982 International) on Solid State Devices, Tokyo Japan 1982, Japanese J. Appl. Phys., vol. 22(1983), Supplement 22-1, pp. 267 - 270
  20. K. Yamaguchi "A mobility model for carriers in the MOS inversion layer", IEEE Trans. Electron Devices, vol. ED-30, no. 6, pp. 658 - 663, June 1983
  21. K. Yamaguchi, "A time-dependent and two-dimensional numerical model for MOSFET device operation", Solid-State Electronics, vol. 26, no. 9, pp. 907 - 916, 1983
  22. 山口 憲, 浅井 彰二郎, 小沢 時典, 横溝 剛一, "プロセス, デバイス, 回路・統合シミュレ－ション実験 (Experimentation with Integrated Process, Device and Circuit Simulators)"電子通信学会論文誌(C), vol. J66-C, no. 12, pp. 1124 - 1131, 1983年12月
  23. M. Horiuchi, K. Yamaguchi and T. Kaga, "FCAT-II：A 50 ns/15 V alterable nonvolatile memory devices - Part II：Analysis", IEEE Trans. Electron Devices, vol. ED-31, no. 6, pp. 739 - 746, June 1984
  24. K. Yamaguchi, "Mathematical modeling of semiconductor-on-insulator (SOI) device operation", IEEE Trans. Electron Devices, vol. ED-31, no. 7, pp. 977 - 982, July 1984
  25. M. Horiuchi and K. Yamaguchi, "SOLID: High-voltage, high-gain 300 nm channel-length MOSFETs - I. Simulation", Solid-State Electronics, vol. 28, no. 5, pp. 465 - 472, 1985
  26. K. Yamaguchi, R. Nishimura, T. Hagiwara and H. Sunami, "Two-dimensional numerical model of memory devices with a corrugated capacitor cell structure", IEEE Trans. Electron Devices, vol. ED-32, no. 2, pp. 282 - 289, Feb. 1985, Joint special issue with IEEE J. Solid-State Circuits, vol. SC-20, no. 1, pp. 202 - 209, 1985
  27. H. Sunami, T. Kure, K. Yagi, Y. Wada, K. Yamaguchi, H. Miyazawa and S. Shimizu, "Scaling considerations and dielectric breakdown improvement of a corrugated capacitor cell for a future dRAM", IEEE Trans. Electron Devices, vol. ED-32, no. 2, pp. 296 - 303, Feb. 1985, Joint special issue with IEEE J. Solid-State Circuits, vol. SC-20, no. 1, pp. 216 - 223, 1985
  28. M. Horiuchi and K. Yamaguchi, "SOLID II: High-voltage, high-gain kilo-Angstrom-channel-length CMOSFET's using silicide with self-aligned ultlashallow (3S) junction", IEEE Trans. Electron Devices, vol. ED-33, no. 2, pp. 260 - 269, Feb. 1986
  29. K. Yamaguchi, "An extended stream-function method for computer analysis of nonplanar structures", Solid-State Electronics, vol. 29, no. 11, pp. 1129 - 1136, 1986
  30. K. Yamaguchi, T. Ohtoshi, C. Kanai-Nagaoka, T. Uda, Y. Murayama and N. Chinone, "Two-dimensional device simulator for laser diodes: HILADIES", Electronics Letters, vol. 22, no. 14, pp. 740 - 741, July 1986
  31. T. Ohtoshi, K. Yamaguchi, C. Nagaoka, T. Uda, Y. Murayama and N. Chinone, "A Two-dimensional device simulator of semiconductor lasers", Solid-State Electronics, vol. 30, no. 6, pp. 627 - 638, 1987
  32. 三島 信子, 山口 憲, "pバッファ層付きGaAs MESFETの2次元解析" 電子情報通信学会論文誌(C), Vol. J70-C, no. 5, pp. 631 - 636, 1987, Translated to English by Scripta Technica, Inc., Electronics and Communications in Japan, Part II ,vol. 71, no. 4, pp. 19 - 25, April 1988, N. Mishima and K. Yamaguchi, "A two-dimensional numerical analysis of GaAs MESFETs with a p-buffer layer" Trans. IEICE Japan, vol. J-70-C, no. 4, 631 - 636, May 1987
  33. T. Ohtoshi, K. Yamaguchi and N. Chinone, "Analysis of astigmatism in high-power semiconductor lasers", Japan J. Appl. Phys., vol. 26, no. 1, pp. L68- L70, January 1987
  34. H. Mizuta, K. Yamaguchi and S. Takahashi, "Surface potential effect on gate-drain avalanche breakdown in GaAs MESFET's", IEEE Trans. Electron Devices, vol. ED-34, no. 10, pp. 2027 - 2033, Oct. 1987
  35. K. Yamaguchi and Y. Shiraki, "Computer simulation of a new MESFET with an atomic-layer-doped structure", IEEE Trans. Electron Devices, vol. ED-35, no. 11, pp. 1909 - 1914, Nov. 1988
  36. A. A. van Gorkum, and K. Yamaguchi, "Classical calculations of CV profiles for atomic layer doping structures in silicon", IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 410 - 415, Feb. 1989
  37. T. Ohtoshi, K. Yamaguchi and N. Chinone, "Analysis of current leakage in InGaAsP/InP buried heterostructure lasers", IEEE J. Quantum Electronics, vol. 25, no. 6, pp. 1369 - 1375, June 1989
  38. H. Mizuta, K. Yamaguchi, M. Yamane, T. Tanoue and S. Takahashi, "Two-dimensional numerical simulation of Fermi-level pinning phenomena due to DX centers in AlGaAs/GaAs HEMTs", IEEE Trans. Electron Devices, vol. 36, no. 10, pp. 2307 - 2314, Oct. 1989
  39. Patrick D. Rabinzohn, T. Usagawa, H. Mizuta, and K. Yamaguchi, "The new two-dimensional electron gas base HBT (2DEG-HBT): Two-dimensional numerical simulation", IEEE Trans. Electron Devices, vol. 38, no. 2, pp. 222 -231, February 1991
  40. H. Kurino, H. Kiba, H. Mori, S. Yokoyama, K. Yamaguchi and M.Koyanagi, "Coupled Monte Carlo-energy relaxation analysis of hot carrier light emission in metal oxide semiconductor field effect transistor's", Japan. J. Appl. Phys., vol. 30, no. 12B, pp. 3666 - 3670, December 1991
  41. A. Sawada, T. Usagawa, S. Ho and K. Yamaguchi, "Possible new structure for one-dimensional electron-gas systems by interface bending of n-AlGaAs/u-GaAs heterojunctions", Appl. Phys. Lett., vol. 60, no. 12, pp. 1492 - 1494, March 1992
  42. S. Ho and K. Yamaguchi, "Effects of reservoirs on quantum transport phenomena in mesoscopic systems", Semicond. Sci. Technol., vol. 7, pp. B430 - B433, 1992, IOP Publishing Ltd.
  43. C. Kusano, H. Masuda, K. Mochizuki, H. Mizuta and K. Yamaguchi, "Simulation of the effect of emitter doping on the delay time in AlGaAs/GaAs heterojunction bipolar transistors", Jpn. J. Appl. Phys., vol. 31(1992) pp. L1650 - L1653, Part 2. no. 12A, 1 December 1992
  44. S. Ho, A. Moriyoshi, I. Ohbu, O. Kagaya, H. Mizuta and K. Yamaguchi, "Theoretical analysis of transconductance enhancement caused by electron-concentration-dependent screening in heavily doped systems", IEICE Trans. Electron., vol. E77-C, no. 2, pp. 155 - 160, February 1994
  45. S. Ho, M. Oohira, O. Kagaya, A. Moriyoshi, H. Mizuta and K. Yamaguchi, "Dynamic simulation of multiple trapping processes and anomalous frequency dependence in GaAs MESFETs", IEICE Trans. Electron., vol. E77-C, no. 2, pp. 187 - 193, February 1994
  46. Philippe Jansen, Hiroshi Mizuta, Ken Yamaguchi and Mathias Wagner, "Theoretical Study of Tunneling Current in the Access Region of Various Heterojunction Field-Effect Transistor Structures", J. Appl. Phys, vol. 79, pp. 3603 - 3607, April 1, 1996
  47. M. Horiuchi, T. Teshima, K. Tokumasu, and K. Yamaguchi, "High-current small-parasitic-capacitance MOSFET on a poly-Si interlayered (PSI: Ψ) SOI wafer", IEEE Trans. Electron Devices, vol. 45, no. 5, pp. 1111 - 1115, May 1998
  48. K. Yamaguchi, T. Teshima, and H. Mizuta, "Numerical analysis of an anomalous current assisted by locally generated deep traps in pn junctions", IEEE Trans. Electron Devices, vol. 46, no. 6, pp. 1159 - 1165, June 1999
  49. L. S. Geux and K. Yamaguchi, "Modeling and characterization of a strained Si/Si1-xGex transistor with δ-doped layers" Journal of Applied Physics, vol. 86, no. 3, pp.1443 - 1448, 1 August 1999
  50. K. Yamaguchi, "Theoretical study of deep-trap-assisted anomalous currents in worst-bit cells of dynamic random-access memories (DRAMs)", IEEE Trans. Electron devices, vol. 47, no. 4, pp. 774 - 780, April 2000
  51. K. Yamaguchi, "Temperature dependence of anomalous currents in worst-bit cells in dynamic random-access memories" Journal of Applied Physics, vol. 87, no. 11, pp. 8064 - 8069, 1 June 2000
  52. Ken Yamaguchi "Modeling and characterization of polycrystalline-silicon TFTs with a channel-length comparable to a grain-size" Journal of Applied Physics, vol. 89, no. 1, pp. 590 - 595, January 1, 2001
  53. Ken Yamaguchi, "On-voltage analysis of a forward-biased pn-junction: an interconnect model for CMOS device simulation", Solid-State Electronics, vol. 46, no. 6, pp. 807 - 817, June 2002
  54. K. Yamaguchi, Y. Takemura, K. Osada, K. Ishibashi, and Y. Saito "3-D device modeling for SRAM soft-error immunity and tolerance analysis", IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 378 - 388, March 2004
  55. K. Osada, K. Yamaguchi, Y. Saito, and T. Kawahara, "SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect", IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 827 - 833, May 2004
  56. Ken Yamaguchi and Masatada Horiuchi, "Capacitance analysis of devices with electrically floating regions", Solid-State Electronics, vol. 48, issue 12, pp. 2115 - 2124, December 2004, ISSN 0038-1101
  57. 長田 健一, 山口 憲, 河原 尊之, 斉藤 良和, "SRAMの宇宙線中性子によるマルチエラー解析及びマルチエラー低減技術", (招待論文) 電子情報通信学会論文誌 C, vol. J90-C, no. 6, pp. 457 - 464, 2007
  58. Ken Yamaguchi, Yoshiaki Takemura, Kenichi Osada, and Yoshikazu Saito, "Bipolar-Mode multibit soft-error-mechanism analysis of SRAMs by three-dimen￢sional device simulation", IEEE Trans. Electron Devices, vol. 54, no.11, pp. 3007 - 3017, November 2007
  59. Ken Yamaguchi, Shogo Sakurai and Kazutaka Tomizawa, "An accurate and simplified modeling of energy and momentum relaxation rates for metal-oxide- semiconductor device simulation", Japan. J. Appl. Phys., vol. 49, (2010) 024303

国内研究会発表（抜粋）

  1. 桜井 清吾, 朱 日明, 佐藤 昌宏, 山口 憲,"次世代半導体デバイス３次元シミュレータの開発(1) －強安定収束シミュレータの開発－", 応用物理学会分科会, シリコンテクノロジー, pp. 26 -31, No. 105, 13th&14th, Nov. 2008, 東京
  2. 朱 日明, 佐藤 昌宏, 桜井 清吾, 山口 憲,"次世代半導体デバイス３次元シミュレータの開発(2) －立体構造の容易生成と高品質メッシュシステム－", 応用物理学会分科会, シリコンテクノロジー, pp. 32 -35, No. 105, 13th&14th, Nov. 2008, 東京